This invention relates generally to multiplexing analog signals onto a common bus and, more particularly, to a current mode analog video bus for a device, such as an imager, and a method thereof
Modern, solid-state, visible light imaging devices have found their way into a variety of consumer, scientific, industrial, medical and military cameras over the last thirty years or so. (These devices include the entire class of solid-state, silicon, visible light imagers including charge coupled devices (CCD""s), charge injection devices (CID""s) and CMOS imagers.) Over this period of time, these devices have exhibited several important trends that have only accelerated in the past decade and are discussed below.
One trend is towards increasing the size of the image array (i.e. total number of pixels per frame). This trend towards larger arrays is driven by new application requirements, the increasing prevalence of computers, and the increasing resolution of electronic displays. This trend has been enabled by advances in integrated circuit fabrication technology.
Another trend is towards increasing the number of frames per second. This trend is especially true for industrial and scientific applications where high throughput and transient event capture are key areas of concern.
Another trend is towards higher levels of integration on the image chip itself. The industry is in the early stages of having a camera on an image chip. As early as 1991, university researchers in Scotland were reporting work on a 312 by 287 pixel xe2x80x98single-chip cameraxe2x80x99, as disclosed in xe2x80x9cVideo Image On a Chipxe2x80x9d, David Scott, Popular Science, September 1991, which is herein incorporated by reference. This trend toward system level integration on to a single chip is driven by cost, a desire for smaller devices, and the expanding markets for digital imagers. Again, this trend has been enabled by advances in fabrication technology, specifically the drive toward smaller minimum feature sizes.
Another trend is towards lower power. This trend is driven by the increasing demand for digital still cameras and digital video cameras which rely on batteries for power. This particular trend reflects a trend in electronics generally.
Another similar trend is towards lower voltage. As fabrication technologies tend toward smaller feature sizes, the devices can withstand lower and lower voltages. As a result, it is only a matter of time before the supply voltages drop from the now common 5 volts for 0.5 xcexcm CMOS technology to 2.5 volts and then 1.0 volt for the next generation technologies.
Yet another trend is towards lower cost. This trend goes hand-in-hand with higher levels of integration and is a driver for decreases in process feature size.
Yet another trend is towards application ease. This trend is less obvious than the others discussed above, but is a natural extension of increasing levels of integration. As circuits become more dense and camera functions are more readily available as part of the imager, the ease of designing a camera with a modem imager becomes much easier.
One of the problems created by a combination of these trends is with analog bandwidth. More specifically, the trend toward larger arrays (i.e. more pixels per frame) and higher frame rates requires that the video output bandwidth, or pixels per second, increase proportionately. For example, a small, relatively slow imager having a resolution of 256xc3x97256 and a frame rate of 10 frames per second need only produce video at greater than 0.66 Mpixels per second. However, a modern mega-pixel imager for industrial or medical applications might have a resolution of 1,024xc3x971,024 and a frame rate of 60 frames per second. Such a camera would need to produce video at 70-80 Mpixels per second (depending on overhead). Many existing devices cannot readily achieve these high analog video bandwidths through a single analog output port and so compromises must be made. As such, depending on the camera design constraints, the analog bandwidth limitation of the imaging device represents an upper limit on array size, frame rate or both.
Most mega-pixel image sensors, including both CCD imagers and Active Pixel Sensor (APS) type CMOS imagers, have a maximum pixel rate inadequate to meet the frame rate needs of higher end applications, such as for industrial and scientific and high definition television (HDTV) imaging applications. With respect to CCD imagers, these imagers are limited by both clocking rates and the speeds of the Correlated Double Sampling (CDS) circuitry. Additionally, the higher amplifier bandwidth required for high pixel rates for these mega pixel image sensors results in increased levels of noise. With respect to the column parallel nature of CMOS imagers, the amplifier and CDS in these imagers can be run at the line rate, rather than the pixel rate, which is generally much easier to achieve. However, the video bandwidth constraints for CMOS imagers come in terms of the multiplexing speed. CMOS imagers typically multiplex their column signals onto a common analog video bus in a sequential fashion. The more columns that are multiplexed or switched onto the bus, the greater the capacitive load that the bus presents to each column amplifier. Therefore, as more columns are connected to the bus, the bandwidth of the bus is reduced. Alternatively, greater power is needed to charge and discharge the bus with its associated capacitance to maintain bandwidth.
One example of a common video bus with a distributed capacitive load associated with each individual column switch is illustrated in FIG. 1. In order for each amplifier 100 to accurately transfer the pixel value from the array 101 represented by a voltage signal onto the common video bus 102, each amplifier 100 must charge or discharge the bus 102 within one pixel time constant. The voltage signal must be stable long enough for a sample and hold circuit (or similar) to accurately present the resultant signal to an analog to digital converter (ADC) (not shown). Typically, at least 5xcfx84 (tau or time constants) are needed to accurately allow the common video bus 102 to settle the voltage signal presented by each individual column amplifier 100.
At higher video bus speeds the individual column amplifier 100 is unable to properly charge or discharge the common video bus 102 resulting in a loss of amplitude which is perceived as a loss of contrast ratio in the video image. At higher pixel element rates where the contrast ratio is compromised, the individual column amplifier characteristic and the video switch characteristics begin to affect the resultant video. The individual column amplifiers 100 will have slightly different offsets with slightly different drive capabilities and each video switch will have slightly different resistances and slightly different thresholds. This combination of column amplifier and video switch characteristics results in each column amplifier having different time constants relative to charging and discharging the video bus. The column amplifier and video switch are common to every pixel in that column. Thus, variations in the video switch characteristics result in what appears to be column based Fixed Pattern Noise (FPN). As more columns are added, each video switch adds more associated capacitance due to the source and drain junctions of MOSFET transistors (or due to the corresponding junctions of bipolar transistors).
In order to overcome the constraints, some designers of CCD""s and APS sensors have resorted to dividing up an imager 104 into halves, quarters 104(1)-104(4), or smaller groupings of sub-imagers, jammed together, as shown in FIG. 2. The signals from each of these sub-imagers 104(1)-104(4) is brought out to its own output port 106(1)-106(4). This approach has been used to provide high frame rate devices, or even to meet standard frame rates with large mega-pixel imagers. In essence, it allows each port 106(1)-106(4) to operate at its maximum pixel rate, but handle fewer pixels in the allotted frame time.
For example, a 1,024xc3x971,024 CMOS imager can increase the number of video busses from one to four and reduce the capacitance of each bus to one-half simply by dividing the imaging array into four arrays of 512xc3x97512 each. In so doing, the overall frame rate may increase by a factor of eight. (Note that the bus capacitance for a CMOS imager scales with the change in the number of columns in a segment, not the number of pixels in the segment. Thus, a 50% capacitance reduction yields a 2xc3x97 speed increase and the 75% reduction in the number of pixels per segment yields a 4xc3x97 speed increase.) However, segmenting the array into subarrays adds system size, complexity, power and cost to handle the multiple analog amplifier chains, i.e. reconstruct the video image off-chip. It also adversely affects application ease for the camera designer. Clearly, this solution is in opposition to many of the trends (i.e. power, cost, application ease, etc.) cited earlier. Further, it is an extremely challenging task to ensure uniformity among each of the independent analog processing chains over all possible pixel rates and temperatures.
This issue has become even more of a problem in recent years as imagers have grown larger, now up to full wafer size. Wafer process variations across an array can lead to further balance problems and even variations in noise characteristics among the subarrays.
An attempt to gain further speed increases by increasing the drive capability of the column amplifiers necessarily increases power dissipation. This is a problem because thermal gradients across the imager may lead to (pixel) dark current shading and gradients in offset and gain among the pixels, which also shows up as a shading effect in the image.
The goal of any attempt to speed up an imager is to increase the frame rate of a given array size, maintain a frame rate while increasing the array size or both. An imager that divides the imaging array into k segments (for this particular example assume that both column and row dimensions are split more or less evenly), will have k output ports wherein the bus capacitance of each port is reduced by a factor equal to the reduction in the number of columns attached to it. For example, a 1 Kxc3x971 K array that has been divided into four sub-arrays of 512xc3x97512 each, will have four sub-busses with xc2xd the capacitance of a single bus for the entire array because the number of columns attached only dropped from 1 K to 512. So the analog bandwidth of each of the ports will only double not quadruple. For a CCD imager, this bandwidth may also be limited by the speed of the CDS circuitry, which typically operates at the (higher) pixel rate as opposed to the (lower) row rate. The overall frame rate of the segmented imager can be increased by a factor of k times the improvement in analog bandwidth. The time required to read out a segment is proportional to the number of pixels in the segment and for the above example this time would be reduced by a factor of four. If the bandwidth of each port doubles, then the array can be read out in one-eighth the time thereby increasing the frame rate by a factor of eight. Note that most of this improvement is due to the reduction in the number of pixels to be read out per port, not to analog bandwidth improvement. The drawback to this approach, of course, is the increase in complexity, power and size that comes from having to reassemble the image or array off-chip.
Another way to view the problems which occur when the frame rate of a given array size is increased, or the frame rate is maintained while increasing the array size, or both, is from the perspective of the terminal variables of the bus capacitance 108(1)-108(12) in FIG. 1. If the bus capacitance is modeled as a single lumped capacitor, the dynamic current i(t) that must be supplied by a given column amplifier is determined by the bus capacitance C, the voltage swing across the capacitor v(t) and the time period of interest dt, or . . .
i(t)=C dv/dt 
Analog bus bandwidth is inversely proportional to i(t). As discussed earlier, analog bandwidth improvement with prior art devices only comes from the way in which the column dimension is divided. Thus, current improvement for the prior art will be equal to or less than the array segmentation factor k. (In the example above it was k/2.)
The present invention has recognized that by transforming the video signal from a voltage domain signal to a current domain signal it is possible to arrange the driving and load impedances such that there is no voltage swing across the bus capacitance (at least in the ideal case). With little or no voltage swing there is little or no need to charge or discharge the bus capacitance. In other words, with the present invention multiplexing of signals on the bus occurs in the current domain so that the bandwidth limiting effects of bus capacitance are minimized because the voltage swing across the bus capacitance is significantly reduced. This transformation can be readily accomplished by using a transconductance amplifier to drive the bus (current output proportional to voltage input) and a transresistance amplifier (voltage output proportional to current input) or other current-input circuit to receive the signal.
A bus system in accordance with one embodiment of the present invention includes at least one common bus for carrying one or more of a plurality of current signals, two or more first switches, and a selector. Each of the first switches has a first position where one of the current signals is coupled to the common bus and a second position where the one of the current signals is disconnected from the common bus. The selector is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions. A dual or differential bus system may also be constructed such that pairs of common busses may be operated in tandem i.e. simultaneously from the same selection circuitry, to multiplex differential signals through the system to a pair of output nodes.
A method for bussing one or more of a plurality of current signals in accordance with another embodiment of the present invention is also provided. In this method, a common bus and a plurality of first switches are provided. Each of the first switches has a first position to couple one of the plurality of current signals to the common bus and a second position to disconnect the one of the plurality of current signals from the common bus. Movement of each of the first switches between the first and second positions is controlled.
An imaging system in accordance with another embodiment of the present invention includes a source of a plurality of current signals, at least one common bus for carrying one or more of the plurality of current signals, two or more first switches, and a selector. Each of the first switches has a first position where one of the current signals is coupled to the common bus and a second position where the one of the current signals is disconnected from the common bus. The selector is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.
A method for bussing one or more of a plurality of current signals in an imaging system in accordance with yet another embodiment of the present invention is also provided. In this method, a plurality of current signals, a common bus and a plurality of first switches are provided. Each of the first switches has a first position to couple one of the plurality of current signals to the common bus and a second position to disconnect the one of the plurality of current signals from the common bus. Next, movement of each of the first switches between the first and second positions is controlled.
A multiple level bus system in accordance with another embodiment of the present invention includes a plurality of first level bus systems, at least one second common bus, two or more second switches, and a second selector. Each of the first level bus systems has at least one first common bus, two or more first switches, and a first selector. The first common bus in each first level bus system carries one or more of a plurality of current signals. Each of the first switches has a first position where one of the current signals is coupled to the first level common bus and a second position where the one of the current signals is disconnected from the first level common bus. The first selector controls the movement of each of the first switches between the first and second positions. The second common bus carries one or more of the plurality of current signals from the first common busses. Each of the second switches has a first position where one of the current signals from one of the first common buses is coupled to the second common bus and a second position where the one of the current signals is disconnected from the second common bus. The second selector controls the movement of each of the second switches between the first and second positions.
A method for multiple level bussing of one or more of a plurality of current signals in accordance with another embodiment of the present invention is also provided. In this method, a plurality of first level bus systems are provided. Each of the first level bus systems comprises a first common bus and a plurality of first switches. Each of the first switches has a first position to couple one of the plurality of current signals to the common bus and a second position to disconnect the one of the plurality of current signals from the common bus. Movement of each of the first switches is controlled between the first and second positions. A second common bus and a plurality of second switches are also provided. Each of the second switches has a first position to couple one of the plurality of current signals from at least one of the first common buses to the second common bus and a second position to disconnect the one of the first common buses from the second common bus. The movement of each of the second switches is controlled between the first and second positions.
One of the advantages of the present invention is that it provides a bus which can better handle the higher analog video bandwidth requirements of imaging devices that have ever increasing image array sizes and increasing numbers of frames per second than prior buses. By way of example only, a bus in accordance with the present invention can handle the bandwidth requirements of an imager with a resolution of 1,024xc3x971,024 and a frame rate of about 60 frames per second.
Another advantage of the present invention is that with the current bus true additive binning is possible. With the present invention, by simply setting the column selection circuitry to simultaneously steer two or more currents to the common bus the currents will be summed. This is an inherent advantage of converting the voltage image signals to current image signals because currents in parallel sum.
Yet another advantage of the present invention is that reasonable values of series resistance which may be introduced by the bus metal and bus switches do not introduce error into the current signal. Thus variations in resistance among the various signals attaching to the bus will not adversely affect output signal uniformity as they might with a voltage mode multiplexing bus when inadequate time is available to fully charge the bus capacitance. Hence, a potential source of fixed pattern noise is eliminated. Of course this holds true as long as the resistance is low enough so that the voltage compliance of the driving current amplifier is not exceeded and that the voltage swing introduced by the series resistance does not become so high that the resultant voltage signals are slowed by the bus capacitance.
Yet another advantage of the present invention is that signal dynamic range may be maintained even as supply voltages inevitably shrink. As supply voltages drop from the now common 5 volts, through the 3.3-volt level and then down through 2.5 volts and below, voltage mode operation will inevitably see a reduction in dynamic range due primarily to the reduction in full-scale voltage. Converting entire signal processing chains from voltage mode operation to current mode operation will permit maintaining dynamic range since, to a first approximation, full scale current is independent of supply voltage. The present invention represents only a portion of the signal processing chain but is essential to maintaining wide dynamic range in a full current mode design particularly where binning will be used.
Yet another advantage of the present invention is application ease and system integration in that high speed multiplexing of analog signals is accomplished with a single output port versus multiple ports thus enhancing overall system integration and eliminating the need for the user to assemble the desired array data off-chip.
Yet another advantage of the present invention is that the technology needed to realize it is compatible with typical microcircuit fabrication processes such as CMOS, BiCMOS, Bipolar, etc. and the chip area required to implement it is comparable to alternative multiplexing schemes that are limited to much lower operating speeds. Thus, the present invention offers higher performance without an area penalty. Since chip area relates proportionally to chip cost, the present invention consequently offers higher performance without a cost penalty.